Alientek DNESP32P4M — An ESP32-P4 board without network connectivity
https://www.cnx-software.com/2025/06/16/alientek-dnesp32p4m-an-esp32-p4-board-without-network-connectivity/

https://redd.it/1lctjhj
@r_riscv

Help me understand the Economics of RISC-V, because I cannot believe it is THIS cheap.

A dinner table conversation this weekend got me to look at the prices of RISC-V based processors, specifically in comparison with any other ISA out there. Are they really that mind-boggingly cheap, or am I missing something?

The system I choose as a foundation for any comparison is the ESP32-C6. If my goal is to build an IoT device, I would prefer a system that comes with BLE and/or WiFi. Some options I found are the Microchip PIC32MZ, Silicon Labs SiWG917, and Silicon Labs EFR32FG22:

||ESP32-C6FH4|PIC32MZ|SiWG917|EFR32FG22|
|:-|:-|:-|:-|:-|
|WiFi|802.11ax|802.11n|802.11ax|\-|
|BLE|5.3|\-|5.4|\-|
|CPU|ESP32-C6|PIC32MZ1|ARM Cortex M4|ARM Cortex M33|
|Flash|4 MiB|2 MiB|4 MiB|512 kiB|
|Price|1,80416 €|4,48000 €|3,11919 €|1,600346 €|

Features are comparable between the ESP32-C6 and SiWG917, but the price difference is significant (73 %). The EFR32 is slightly cheaper but offers much less performance and requires additional components for communications.

Some of the cheapest SoCs (Analog Devices MAX32) out there with comparable computing performance (ARM Cortex M4) cost 4 times as much. Looking at MCUs, the Microchip Technology dsPIC33AK and PIC32AK can be had cheaply (1,10 - 1,80 €) but basically has no memory (128 kiB) or wireless communications. Any MCU with a decent bang (ARM Cortex M4) and memory (>= 1 MiB) will be significantly (> 15 %) more expensive and still require auxiliary chips to do wireless communications.

Just to be toying around with RISC-V, I bought Espressif Systems' development kit (7,65 €), which basically does the same either an Arduino Nano ESP32 (16,90 €) or a Nano 33 IoT (21,81 €) do. How? I mean, I get it, licensing to ARM is expensive and RISC-V being royalty-free is what got me excited in the first place. But come on! Surely it cannot make that much of a difference. What am I missing here or not understanding?

Note: I specifically choose to compare processors for use in embedded applications. I feel like this application allows for more of an apples-to-apples comparison. Processors such as the SiFive P870D or SpacemiT K1 are super exciting but comparing them objectively would be a huge pain - especially if I don't have access to any engineering samples to play with.

Background / Context: I have worked with RISC (SPARC & POWER) for fun as a kid and teenager. Lost track of it growing up, as x86 was dominant in my field (IaaS - SaaS) and I ended up working on the commercial side of things. With the rise of ARM in the mobile world, I paid more attention to RISC and came across RISC-V in the early 2010s. A personal project gave me an excuse to buy some ESP32-C6s and I am currently in the process of digging deeper into RISC-V and related topics. So, I am not exactly and expert or professional.

https://redd.it/1lcuvrg
@r_riscv

Jackett on RISC-V works!

Hi all! I made a script to deploy and run Jackett on my Orange Pi RV2.
https://github.com/Alexgolshtein/Jacket-RISC-V

https://redd.it/1lcvccf
@r_riscv

Question regarding delegation in interrupts

I am confused regarding the delegation part in interrupts

1. There are two places where we can set delegation
a. mideleg register and b. delegation bit in sourcecfg register of APLIC.

Whats the difference between two of them

2. Why do we need a delegation and how is it useful

https://redd.it/1ldtsv9
@r_riscv

Running the classic CDE desktop on RISC-V
https://redd.it/1leam4v
@r_riscv

$3.50 nanoCH57x CH570/CH572 RISC-V development board offers USB-C port, 2.4GHz radio/BLE, and GPIO pins
https://www.cnx-software.com/2025/06/18/3-50-nanoch57x-ch570-ch572-risc-v-development-board-offers-usb-c-port-2-4ghz-radio-ble-and-gpio-pins/

https://redd.it/1lebu4b
@r_riscv

My look at the Orange Pi RV2 - Ky X1 with 8x SpacemiT X60 Cores, but some lacklustre software & doco (IMHO)
https://youtu.be/8fRqIR2PY9c

https://redd.it/1ledew3
@r_riscv

How to get started?

Hey all,

I'm embraking on a new project with RISC-V, but the only computer architecture experience I have is a course on contemporary logic design and a course on systems programming. As a result, I know Vivado and Linux-based C development to some extent. However, in my current project, I have been asked to implement a RISC-V core (specifically Ibex) on an FPGA. The problem is, I have no idea how to set up the core on an FPGA, nor do I know how to upload software on it to run certain programs. I have gone through the documentation of Ibex, but I didn't understand how to get the core on an FPGA. Are there any resources that you would recommend to get me started? Thanks so much.

https://redd.it/1lf8ky7
@r_riscv

How to identify which peripheral caused the interrupt inside the ISR

Example:
I have an external interrupt peripheral(SPI and UART) routed via APLIC. If SPI triggers an interrupt, then assuming it is in a vectored mode. Then the program counter would be PC = stvec(base) + 4 x cause(9 for external interrupt). Then my PC jumps to the ISR location, but inside the ISR, how can I know what caused the interrupt, whether it is SPI or UART?

PC would jump to the same ISR location just based on the cause. So, can I differentiate between the two interrupts(if the cause is the same)

https://redd.it/1lf8xwi
@r_riscv

RVFA Exam

Is it worth to get RVFA Certification?
How tough is the exam?
and What are the benifits of having the certification?

https://redd.it/1lfcr75
@r_riscv

Built a GCC Cross Compiler for RISC-V

Hello All, Got a research project to create a gcc cross compiler that'll output riscv binaries. Wrote a layman friendly research document also. You can access it here: https://github.com/pulkitpareek18/gcc-riscv

If you like this give it a star and don't forget to raise any issue so that it can be improved.

https://redd.it/1lg0ksk
@r_riscv

SOPHGO TECHNOLOGY NEWSLETTER (20250620）

Deploying RISC-V for HPC: China’s First RVAI Cloud Platform Powered by SOPHON Servers

Hi, r/RISCV community, first of all, thanks for your attention and great questions around our SG2044-based RISC-V servers. We’ve noted your interest and are planning a dedicated Q&A session soon.

Meanwhile, we’re excited to share a real-world technical case study: how SG2042-based SOPHON servers are powering China’s first public RVAI (RISC-V + AI) cloud platform, developed by Jiaolong Cloud in Guizhou Province.

 Why RISC-V Matters for Cloud Infrastructure

Ø  Architectural Flexibility – RISC-V’s modularity naturally supports parallel computing workloads, aligning with the industry shift from CPU-centric to GPU/accelerator-driven processing.

Ø  Open Ecosystem – RVAI (RISC-V + AI) offers a transparent alternative to proprietary accelerators, with rapid progress in compiler, runtime, and toolchain support.

Ø  Full-Stack Control – Eliminating licensing barriers enables security-critical deployments without vendor lock-in.

RVCloud: A Real-World Deployment

In 2024, Jiaolong Cloud deployed RISC-V AI infrastructure using SR0-2208-C-A0 and SRM1-20 servers powered by SG2042 chips — creating the first fully operational RVAI public cloud platform in China.

Highlights:

Ø  Single-node integration of general-purpose, HPC, and AI workloads

Ø  Hybrid architecture reducing data movement between compute units

Ø  Production-grade reliability under continuous AI inference loads

 

Hardware Topology

Jiaolong Cloud Platform consists of 21 nodes in total: 9 storage nodes & 12 AI inference nodes 

Platform Architecture

https://preview.redd.it/qt97k9td438f1.png?width=554&format=png&auto=webp&s=e6ecb4abaf9ab116f98f6e6547d73838867db256

Real-World Workloads Enabled

RVCloud currently supports:

Green Computing Centers: Focuses on computing resource optimization and reduced energy consumption.

Science/Education Cloud: RVAI-based platform for research/education resources (includes video network capabilities).

Smart Fire Safety: Uses computer vision (CV) algorithms with camera systems for real-time monitoring and fire safety management.

Vehicle-Road-Cloud: Combines video networks and IoT for automotive applications. Focuses on RISC-V-based foundational software and hardware development.

LLM Inference: Leverages RVAI's cost-efficiency for large model fine-tuning, deployment, and privatization.

 

Appendix: Software Compatibility List

Operating System: Ubuntu, v24.04; Fedora, v38; OpenEuler, v24.03; OpenKylin, v1.0; Debian, v12; Deepin, v23.

Database: OpenSUSE, v20230618; Postgresql, v16.3; OpenBLAS, v3.27; Mariadb, v15.1; MongoDB, V5.0.18; NumPy, v1.24.3; OpenSSL, v3.0.8; Redis, V4.0.14; JeMalloc, v5.3.0.

Computational Library: OpenBLAS, v3.27; NumPy, v1.24.3; OpenSSL, v3.0.8; libjpeg, v2.1.4; libpng, v1.6.37; Openh264, v2.3.1; x265, v3.4; zstd, v1.5.5; opencv, v4.7.0; Eigen3, v3.4.0.

Monitoring &  Visualization Software: Zabbix, v6.4.17; Prometheus, v2.48.1; Grafana, v7.5.15.

Basic Software: Ngnix, v1.23.2; Jboss, v8.0.0; Varnish, v7.0.1; Squid, v5.7; Apache-storm, v2.6.3; Apache-tomcat, v9.0.93; Spark Streaming, v3.5.1; ActiveMQ, v5.18.5; RockerMQ, v5.3.0; Kafka, v3.8.0; Jenkins, v10.0.20; Zookeeper, v3.8.4; Maven, v1.8.0; Kubernetes, v1.26.5; Redis, v4.0.14; K8s, v1.26.5; Dashboard, v2.6.1; JeMalloc, V5.3.0; Mariadb, v15.1;

Frontend Framework Software: Vue, v2.6.12; Vue-count-to, v1.0.13; Vue-cropper, v0.5.5; Vue-meta, v2.4.0; Vue-router, v3.4.9; Vue-draggable, v2.24.3; Vuex, v3.6.0; Element-UI, v2.15.12; Echarts, v5.4.3.

Backend Framework Software: Spring-boot-dependencies, v2.5.15; Druid-spring-boot-starter, v1.2.16; Mybatis-plus, v3.2.0; Spring-boot-starter-websocket, v2.7.12; Spring-boot-maven-plugin, v2.5.15; io.swagger, v1.6.2; Mysql-connector-java, v8.0.23; UserAgentUtils, v1.2.1;

Pagehelper-spring-boot-starter, v1.4.6; Oshi-core, v6.4.4; Commons-io, v2.13.0; Velocity-engine-core, v2.3; Kaptcha, v2.3.3; Fastjson2, v2.0.39; Jjwt, v0.9.1; Jasypt-spring-boot-starter, v2.1.1; Quartz, v2.3.2; Httpclient, v4.5.13.

What technical aspects interest you most about RVAI implementations, and what content do you expect us to deliver? We’ll prioritize your opinions in our following sessions. Leave your comments below!

https://redd.it/1lg48sy
@r_riscv

A gentler introduction to Zicsr

I am implementing a riscv emulator from spec, I am kinda stuck at csr, I am feeling a bit overwhelmed, is there an article/blog which explains csr in a more simplistic terms ?

https://redd.it/1lgq8mt
@r_riscv

RISC-V assembly is basically just a hint as to what machine code to generate

I'm used to the instructions I specify being the instructions that end up in the object file. RISC-V allows the assembler a lot of freedom around doing things like materializing constants. I'm not sure why clang 18 is replacing the addi with a c.mv. I mean it clearly can, and it saves two bytes, but it could also just remove the instruction entirely and save 4 bytes.

Interestingly, clang 21 keeps the addi like gcc does.

ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ cat foo.s
.text
.globl start
start: 
        lui     a2, %hi(0x81000000)
        addi    a2, a2, %lo(0x81000000)
ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ clang --target=riscv64 -march=rv64gc -mabi=lp64 -c foo.s
ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ llvm-objdump -M no-aliases -r -d foo.o

foo.o:  file format elf64-littleriscv


Disassembly of section .text:


0000000000000000 <start>:
       0: 37 06 00 81   lui     a2, 0x81000
       4: 32 86         c.mv    a2, a2
ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ gcc -c foo.s
ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ llvm-objdump -M no-aliases -r -d foo.o


foo.o:  file format elf64-littleriscv


Disassembly of section .text:


0000000000000000 <start>:
       0: 37 06 00 81   lui     a2, 0x81000
       4: 13 06 06 00   addi    a2, a2, 0x0
ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ clang --version
Ubuntu clang version 18.1.3 (1)
Target: riscv64-unknown-linux-gnu
Thread model: posix
InstalledDir: /usr/bin
ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ gcc --version
gcc (Ubuntu 13.2.0-23ubuntu4) 13.2.0
Copyright (C) 2023 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.


ubuntu@em-flamboyant-bhaskara:~/src/rvsoftfloat/src$ 

Here's the output of clang 21 - it seems to want to put things off til later and compress the code with linker relaxation, if possible, which is great, but the 0x81000000 isn't an address. This must be the fault of the %hi() and %lo().

foo.o:file format elf64-littleriscv

Disassembly of section .text:

0000000000000000 <start>:
0: 00000637 lui a2, 0x0
0000000000000000: RRISCVHI20*ABS*+0x81000000
0000000000000000: RRISCVRELAX*ABS*
4: 00060613 addi a2, a2, 0x0
0000000000000004: RRISCVLO12IABS+0x81000000
0000000000000004: RRISCVRELAXABS
% clang --version
clang version 21.0.0git (https://github.com/llvm/llvm-project.git c17ae161fdb713652292d6dff7c9317cbac8bb25)
Target: arm64-apple-darwin24.5.0
Thread model: posix
InstalledDir: /Users/ben/src/llvm-project/build/bin

I *think* but am not sure that these behaviors originate in RISCVMatInt.cpp in llvm, which is an interesting read. It contains the algorithms for materializing constant values.

https://redd.it/1lhg415
@r_riscv

Chips I recommend moving from STM32 to being a RISC-V Shop!
https://youtu.be/dAyygPmpspc?si=bn_VvGzdb8tKwKIk

https://redd.it/1lhykji
@r_riscv

How should I approach learning RISC-V architecture to eventually design my own CPU (using Verilog)?

I'm a 2nd/3rd-year ECE student with a decent understanding of RISC-V assembly (RV32I). I've also worked on small Verilog projects like sequence generators, Fibonacci circuits, ALUs etc.

Now I want to take the next step: understanding the architecture of a RISC-V CPU so I can eventually design and implement one myself — likely using Verilog.

I’ve heard advice like “focus on the architecture first, not the HDL”, which makes sense, but I’m not sure how to structure my learning.

Should I begin by learning the 5-stage pipeline?
Should I start with a single-cycle CPU first?
What are the best resources or projects to learn architectural thinking?
When does the transition to writing Verilog begin?

Any guidance or a step-by-step learning roadmap would really help.

https://redd.it/1lii7a7
@r_riscv

Practical memory & IO hazards

I'm trying to transition my Verilog core from a simulation to an actual circuit on an FPGA. I've created an arbiter for the memory access, but I don't know how to factor the delay in when working out the hazard handling, and every source I could find just says "Oh, split the memories", but that wouldn't really solve the problem...
How is this usually handled?

https://redd.it/1liifj5
@r_riscv

how to get started?

i just got a muse pi pro(a riscv based sbc),how should i start to use it? and i am new in riscv, i want some advice, thanks.

https://redd.it/1lj3a36
@r_riscv

People in the EU, how did you get your hands on a RICS-V board?

Hi everyone, I recently decided to experiment with RISC-V, learn about it and develop some software for it. So I wondered how can I get my hands on a RISC-V board for development in the EU? Is there some online shop or distributor from where I can order some boards?

https://redd.it/1ll36hr
@r_riscv