Open-Source RISC-V Cores with V-Extension Support
I'm researching open-source RISC-V implementations with vector extension (RVV) support for FPGA implementation. And i can't find anything, can anybody help me?
https://redd.it/1ktog0s
@r_riscv
I'm researching open-source RISC-V implementations with vector extension (RVV) support for FPGA implementation. And i can't find anything, can anybody help me?
https://redd.it/1ktog0s
@r_riscv
Reddit
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Bitmask for hstatus
I'm trying to come up with the legal read/write bitmask for hstatus. In the five-embedded hypervisor extension i see this image. You may have to open in new image, it's showing poorly in this editor view.
https://preview.redd.it/j0iqa12zej2f1.png?width=1340&format=png&auto=webp&s=e77c1f08a6a4668fdebdb2a9849f4939b8cb825e
0 - 4 is 0
so this is 5 bits of 0,
VSBE states it's length is 2 indicated by the bottom. All of them seem this way to accurately represent the number except VSBE and SPVP.
Do I need to assume that if its length is two, but the indicated register is only one bit in length. it is paired into the left indicated field? (SPV and SPVP) make sense to be together but that is to the right field, which would mean VSBE pairs with the wpri field?
https://redd.it/1ktpcvt
@r_riscv
I'm trying to come up with the legal read/write bitmask for hstatus. In the five-embedded hypervisor extension i see this image. You may have to open in new image, it's showing poorly in this editor view.
https://preview.redd.it/j0iqa12zej2f1.png?width=1340&format=png&auto=webp&s=e77c1f08a6a4668fdebdb2a9849f4939b8cb825e
0 - 4 is 0
so this is 5 bits of 0,
VSBE states it's length is 2 indicated by the bottom. All of them seem this way to accurately represent the number except VSBE and SPVP.
Do I need to assume that if its length is two, but the indicated register is only one bit in length. it is paired into the left indicated field? (SPV and SPVP) make sense to be together but that is to the right field, which would mean VSBE pairs with the wpri field?
https://redd.it/1ktpcvt
@r_riscv
Saturn Vector unit FPGA
Has anyone tried to develop Saturn Vector unit on FPGA? Can you share synthesis results (how many LUTs, clock frequency, etc.)?
https://redd.it/1ktwi87
@r_riscv
Has anyone tried to develop Saturn Vector unit on FPGA? Can you share synthesis results (how many LUTs, clock frequency, etc.)?
https://redd.it/1ktwi87
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High RISC, High Reward: RISC-V at 15
https://riscv.org/riscv-news/2025/05/risc-v-15-years/
https://redd.it/1ku17cn
@r_riscv
https://riscv.org/riscv-news/2025/05/risc-v-15-years/
https://redd.it/1ku17cn
@r_riscv
Public Review : RISC-V Supervisor Binary Interface (SBI) version v3.0
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/MEUiWE8u7Mw/m/0_qf8ftoAQAJ
https://redd.it/1ku2k5c
@r_riscv
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/MEUiWE8u7Mw/m/0_qf8ftoAQAJ
https://redd.it/1ku2k5c
@r_riscv
GCC 16 Lands Better Support For -march= Targeting On RISC-V
https://www.phoronix.com/news/GCC-16-Better-march-RISC-V
https://redd.it/1kune1p
@r_riscv
https://www.phoronix.com/news/GCC-16-Better-march-RISC-V
https://redd.it/1kune1p
@r_riscv
Phoronix
GCC 16 Lands Better Support For -march= Targeting On RISC-V
Merged on Friday for the GCC 16 compiler is better handling of the '-march=' compiler option on RISC-V systems when seeing multiple -march= hits and wanting to specify the RISC-V CPU name for targeting.
Innatera T1 neural processor
Innatera, a Dutch startup, their T1 neuromorphic microcontroller does fast pattern recognition based on spiking neural networks (sub-1mW power usage).
The interface in the SNP (Spiking Neural Processor) is provided by a 32-bit RISC-V core with floating point and 384 KB of embedded SRAM.
It is in a tiny 2.16mm x 3mm, 35-pin WLCSP package.
Their SDK (Software Development Kit) has an API (Application Programming Interface) for pytorch (An optimized tensor library for deep learning).
https://innatera.com/products/spiking-neural-processor-t1
(<scarcism>Only 799 more iterations until Cyberdyne Systems can finally release their fabled RISC-V powered army of T-800's 🤖🤖🤖🤖🤖</scarcism>)
https://redd.it/1kvlkz6
@r_riscv
Innatera, a Dutch startup, their T1 neuromorphic microcontroller does fast pattern recognition based on spiking neural networks (sub-1mW power usage).
The interface in the SNP (Spiking Neural Processor) is provided by a 32-bit RISC-V core with floating point and 384 KB of embedded SRAM.
It is in a tiny 2.16mm x 3mm, 35-pin WLCSP package.
Their SDK (Software Development Kit) has an API (Application Programming Interface) for pytorch (An optimized tensor library for deep learning).
https://innatera.com/products/spiking-neural-processor-t1
(<scarcism>Only 799 more iterations until Cyberdyne Systems can finally release their fabled RISC-V powered army of T-800's 🤖🤖🤖🤖🤖</scarcism>)
https://redd.it/1kvlkz6
@r_riscv
Innatera
Spiking Neural Processor T1
How hard it is to design your own ISA?
As title, how hard is it really to design a brand new Instruction Set Architecture from the ground up? Let's say, hypothetically, the goal was to create something that could genuinely rival RISC-V in terms of capabilities and potential adoption.
Could a solo developer realistically pull this off in a short timeframe, like a single university semester?
My gut says "probably not," but I'd like to hear your thoughts. What are the biggest hurdles? Is it just defining the instructions, or is the ecosystem (compilers, toolchains, community support) the real beast? Why would or wouldn't this be feasible?
Thanks.
https://redd.it/1kvo1ln
@r_riscv
As title, how hard is it really to design a brand new Instruction Set Architecture from the ground up? Let's say, hypothetically, the goal was to create something that could genuinely rival RISC-V in terms of capabilities and potential adoption.
Could a solo developer realistically pull this off in a short timeframe, like a single university semester?
My gut says "probably not," but I'd like to hear your thoughts. What are the biggest hurdles? Is it just defining the instructions, or is the ecosystem (compilers, toolchains, community support) the real beast? Why would or wouldn't this be feasible?
Thanks.
https://redd.it/1kvo1ln
@r_riscv
Reddit
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Linux 6.15 Release Main changes, Arm, RISC-V and MIPS architectures - CNX Software
https://www.cnx-software.com/2025/05/26/linux-6-15-release-main-changes-arm-risc-v-and-mips-architectures/
https://redd.it/1kw8395
@r_riscv
https://www.cnx-software.com/2025/05/26/linux-6-15-release-main-changes-arm-risc-v-and-mips-architectures/
https://redd.it/1kw8395
@r_riscv
Reddit
From the RISCV community on Reddit: Linux 6.15 Release Main changes, Arm, RISC-V and MIPS architectures - CNX Software
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ELI5- Stack, SP, FP
Hi everyone in a few week I'm starting midterms, and I have an exam on riscv.
The only thing I can't get in my head is how, why, and where should I use the Stack-related registry. I often see them used when a function is starting or closing, but I don't know why.
Can anyone help me? Thanks
https://redd.it/1kwjp4g
@r_riscv
Hi everyone in a few week I'm starting midterms, and I have an exam on riscv.
The only thing I can't get in my head is how, why, and where should I use the Stack-related registry. I often see them used when a function is starting or closing, but I don't know why.
Can anyone help me? Thanks
https://redd.it/1kwjp4g
@r_riscv
Reddit
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I made an interactive RISC-V Web Simulator using react flow
https://riscv-simulator-five.vercel.app/
https://redd.it/1kwpm74
@r_riscv
https://riscv-simulator-five.vercel.app/
https://redd.it/1kwpm74
@r_riscv
riscv-simulator-five.vercel.app
Interactive RISC-V Simulator
A web-based interactive RISC-V processor simulator for visualizing. Write and execute RISC-V assembly code, observe register changes, and track instruction flow.
FYI: RISC-V Summit Europe 2025 Videos are up on YouTube...
https://www.youtube.com/watch?v=rFZFgCXNCSg&list=PL85jopFZCnbPT2XeIt4qPwC4alGvQfMcL
https://redd.it/1kxsxen
@r_riscv
https://www.youtube.com/watch?v=rFZFgCXNCSg&list=PL85jopFZCnbPT2XeIt4qPwC4alGvQfMcL
https://redd.it/1kxsxen
@r_riscv
YouTube
Contribution towards European sovereignty for embedded processors
Prebuilt GNU toolchain with Vector Extension enabled
Hi,
Current pre-built toolchain by riscv-collab does not enable Vector Extension by default.
I’ve just modified the workflows to enable it. You can download the prebuilt toolchain from https://github.com/haipnh/riscv-gnu-toolchain_gcv/releases. There are 24 options to be used.
I have free account so I’ll update it once a month. Enjoy!
https://redd.it/1kxyi1q
@r_riscv
Hi,
Current pre-built toolchain by riscv-collab does not enable Vector Extension by default.
I’ve just modified the workflows to enable it. You can download the prebuilt toolchain from https://github.com/haipnh/riscv-gnu-toolchain_gcv/releases. There are 24 options to be used.
I have free account so I’ll update it once a month. Enjoy!
https://redd.it/1kxyi1q
@r_riscv
GitHub
Releases · haipnh/riscv-gnu-toolchain_gcv
Contribute to haipnh/riscv-gnu-toolchain_gcv development by creating an account on GitHub.
FLEXING RISC-V INSTRUCTION SUBSET PROCESSORS (RISPS) TO EXTREME EDGE
https://arxiv.org/pdf/2505.04567
https://redd.it/1ky0v0d
@r_riscv
https://arxiv.org/pdf/2505.04567
https://redd.it/1ky0v0d
@r_riscv
US curbs chip design software, chemicals, other shipments to China
https://www.reuters.com/world/china/trump-tells-us-chip-designers-stop-selling-china-ft-reports-2025-05-28/
https://redd.it/1ky350i
@r_riscv
https://www.reuters.com/world/china/trump-tells-us-chip-designers-stop-selling-china-ft-reports-2025-05-28/
https://redd.it/1ky350i
@r_riscv
Reuters
US curbs chip design software, chemicals, other shipments to China
The United States has ordered a broad swathe of companies to stop shipping goods to China without a license and revoked licenses already granted to certain suppliers, said three people familiar with the matter.
Learning riscv
I am trying to learn riscv. I am a complete beginner. Anyone have any recommendations for a good source I can study it from?
https://redd.it/1kyjypv
@r_riscv
I am trying to learn riscv. I am a complete beginner. Anyone have any recommendations for a good source I can study it from?
https://redd.it/1kyjypv
@r_riscv
Reddit
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Apple is adding Mach-O's riscv32 support to LLVM
https://github.com/llvm/llvm-project/pull/141682
https://redd.it/1kyvcmn
@r_riscv
https://github.com/llvm/llvm-project/pull/141682
https://redd.it/1kyvcmn
@r_riscv
GitHub
[RISCV] Add basic Mach-O triple support. by fpetrogalli · Pull Request #141682 · llvm/llvm-project
Based on a patch written by Tim
Northover (https://github.com/TNorthover).
Northover (https://github.com/TNorthover).
How is virtualization mode achieved in Riscv ?
Hi
I was reading the privilege spec of Riscv. In chapter 21.1 it says the "the current virtualization mode, denoted V, indicates whether the Hart is currently executing in a guest. When V=1, the Hart is either in virtual S-mode(VS-mode) or in virtual U-mode(VU-mode) atop a guest running in VS-mode"
My question is "this V bit" is part of which CSR? how do I monitor this? Or is it implicitly set ?
Through out the hypervisor section it says when V=1 something happens, when V=0 something happens....
But what qualifies as V=1? How do I make V=1.
Any hint much appreciated. Thanks!
https://redd.it/1kyymv6
@r_riscv
Hi
I was reading the privilege spec of Riscv. In chapter 21.1 it says the "the current virtualization mode, denoted V, indicates whether the Hart is currently executing in a guest. When V=1, the Hart is either in virtual S-mode(VS-mode) or in virtual U-mode(VU-mode) atop a guest running in VS-mode"
My question is "this V bit" is part of which CSR? how do I monitor this? Or is it implicitly set ?
Through out the hypervisor section it says when V=1 something happens, when V=0 something happens....
But what qualifies as V=1? How do I make V=1.
Any hint much appreciated. Thanks!
https://redd.it/1kyymv6
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Reddit
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orange pi rv2 gpu acceleration
has anyone gotten gpu acceleration running on the orange pi rv2? its using an imagination bxe-2-32. ive installed mesa and vulkan for it but it still says its rendering using llvmpipe. was wondering if theres anyway to enable yet.
https://redd.it/1kz493p
@r_riscv
has anyone gotten gpu acceleration running on the orange pi rv2? its using an imagination bxe-2-32. ive installed mesa and vulkan for it but it still says its rendering using llvmpipe. was wondering if theres anyway to enable yet.
https://redd.it/1kz493p
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Reddit
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