RIML Lab

🚀 Research Internship Opportunities
We are seeking highly motivated interns or collaborators for upcoming research projects in the areas of Low-Level Hardware Design and Multi-Agent Large Language Models (LLMs). The goal is to produce high-quality research with potential for submission to top-tier conferences or journals.

🤖 Position — LLM & Multi-Agent Research Intern
Focus: Multi-Agent Systems, Large Language Models, and LLM Orchestration
Technical Requirements:
• Proficiency in Python and PyTorch
• Familiarity with transformers, LangChain, vLLMs, or agent frameworks
• Experience with Git and working with academic codebases
• Basic understanding of Machine Learning

🔧 Position — Low-Level Hardware Intern
Focus: Verilog / SystemVerilog, FPGA-based Systems, and Hardware Acceleration
Technical Requirements:
• Strong knowledge of digital logic design
• Hands-on experience with Verilog or SystemVerilog
• Familiarity with FPGA toolchains (e.g., Vivado, ModelSim)
• Comfortable reading and adapting low-level academic GitHub repositories
• Clean and modular hardware coding practices

📌 General Requirements (All Positions)
• English proficiency
• Independent, resilient, and willing to commit serious time
• Able to work in a fast-paced, research-oriented environment
• Passionate about learning new tools and solving challenging problems
• On-call availability and a strong sense of accountability

📨 To Apply:
Please fill out this form completely and upload your CV.

📅 Application Deadline: May 15, 2025

📚 For relevant background reading, please see:
1. https://arxiv.org/abs/2412.07822
2. https://arxiv.org/abs/2503.16528

arXiv.org

MAGE: A Multi-Agent Engine for Automated RTL Code Generation

The automatic generation of RTL code (e.g., Verilog) through natural language instructions has emerged as a promising direction with the advancement of large language models (LLMs). However,...

www.tg-me.com/sg/telegram/com.RIMLLab/184

2.9K viewsAmir Kasaei, edited  May 9 at 20:13

🚀 Research Internship Opportunities
We are seeking highly motivated interns or collaborators for upcoming research projects in the areas of Low-Level Hardware Design and Multi-Agent Large Language Models (LLMs). The goal is to produce high-quality research with potential for submission to top-tier conferences or journals.

🤖 Position — LLM & Multi-Agent Research Intern
Focus: Multi-Agent Systems, Large Language Models, and LLM Orchestration
Technical Requirements:
• Proficiency in Python and PyTorch
• Familiarity with transformers, LangChain, vLLMs, or agent frameworks
• Experience with Git and working with academic codebases
• Basic understanding of Machine Learning

🔧 Position — Low-Level Hardware Intern
Focus: Verilog / SystemVerilog, FPGA-based Systems, and Hardware Acceleration
Technical Requirements:
• Strong knowledge of digital logic design
• Hands-on experience with Verilog or SystemVerilog
• Familiarity with FPGA toolchains (e.g., Vivado, ModelSim)
• Comfortable reading and adapting low-level academic GitHub repositories
• Clean and modular hardware coding practices

📌 General Requirements (All Positions)
• English proficiency
• Independent, resilient, and willing to commit serious time
• Able to work in a fast-paced, research-oriented environment
• Passionate about learning new tools and solving challenging problems
• On-call availability and a strong sense of accountability

📨 To Apply:
Please fill out this form completely and upload your CV.

📅 Application Deadline: May 15, 2025

📚 For relevant background reading, please see:
1. https://arxiv.org/abs/2412.07822
2. https://arxiv.org/abs/2503.16528

BY RIML Lab